1. Technical Field
The present disclosure relates to the memory repairing technology. More particularly, the present disclosure relates to the memory repairing technology that uses a spare memory to cover the faulty cell addresses in a main memory.
2. Description of Related Art
The International Technology Roadmap for Semiconductors (ITRS) from 2001 to 2007 predicts that the embedded memory will occupy 94% of the entire system memory market before 2014. Although the data is modified at 2009, it is still larger than 87%. In recent years, the production value of the memory occupies more than 30% of the entire production value of the semiconductor chips.
However, since not only the growth of the memory capacity often breaks the Moore's law, but also the variance increases extremely due to the nanotechnology, the yield of the memory without being repaired is lower than 20%. To improve the yield and lower the cost, the memory repairing technology is needed.
The related prior technologies are described as follows.
A conventional memory repairing technology at an early stage is performed using the laser to burn out some preset fuses, and thus a de-multiplexer is controlled to select the word-line of the spare row memory for covering the original word address. The technology needs to design the fuse and to use an extra laser device. Therefore, the technology is not suitable for use in the embedded memory and large capacity memory. In recent years, a iii remapping technology has been applied gradually to replace the conventional memory repairing technology at the early stage.
Referring to FIG. 1, FIG. 1 is a schematic view of the architecture of a conventional memory address remapping circuit, wherein the conventional memory address remapping circuit is an embedded memory repairing circuit. Besides having a main memory 110 with a column address decoder and a row address decoder, the conventional memory address remapping circuit applies a binary content-addressable memory (BCAM) 120 to compare the faulty cell address of the main memory and the spare memory in parallel. If the address in the spare memory matches (also called hits) the faulty cell address, a priority encoder is applied to select a word line (WL) of the spare memory 130 to replace the accessing of the faulty cell address by controlling a multiplexer 140. The drawback of the technology is low repair rate.
The repairing technologies by using two-dimensional architecture, such as a built-in spare row and column replacement analysis system for embedded memories (U.S. Pat. No. 6,304,989), are focused on improving the repair rate by analyzing the distribution of the faulty cell addressed. In detail, the technology takes the spare row and the spare column into consideration, and thus has better repair rate than the conventional technologies that use one-dimensional architecture. However, the repairing technology performs poorly to deal with the clustered faults. As described above, the growth of the memory capacity and variance makes the two-dimensional architecture also perform poorly.
In Taiwan patent application number 200921690 filed on May 16, 2009, a memory remapping architecture is disclosed to deal with the clustered faults by base address shifting. In detail, the spare memory array provides subarrays in row, column or square shapes to repair the clustered faults. However, the architecture can only deal with array faults on continuous plane, but not to deal with the scattered address fault caused by errors of one or multiple address lines. Therefore, the drawbacks can be listed as follows:
First, the architecture cannot be established in an embedded memory effectively, or else the repair rate is low when applying the algorithm in an embedded memory directly.
Second, the architecture still performs poorly to deal with the scattered faults caused by word line defect.
A paper entitled “Efficient BISR Techniques for Embedded Memories Considering Cluster Faults” is published in the IEEE Transaction on VLSI journal in February 2010. The author takes the cluster faults into consideration, and provides an effective repairing architecture including the divided word line (DWL), the divided bit line (DBL) or both. However, the architecture causes some performance impacts on the memory. On the other hand, the divided spare column and row of the architecture performs poor repair rate to the scattered address faults caused by the address line defects.